The present invention relates to a wiring board used in electronic equipment and a method of producing the wiring board, and more particularly to a wiring board for mounting electronic devices with high-density terminals and a method of production thereof.
In a conventional thick-film wiring board fabrication method, inter-layer insulation materials and wiring materials are alternately stacked, and are baked at the same time. For example, a green sheet is used as the inter-layer insulation material and a conductive paste is used as the wiring material.
In a conventional thick-film wiring board, wiring patterns and electrodes cover the entire area of the wiring board according to the same basic wiring lattices.
In the conventional thick-film wiring board, the interlayer insulation material contracts during baking. With such contraction, the wiring material also contracts. Under the current technology, controlling this contraction during fabrication is limited (e.g., an error of approximately 0.2% of the target size).
Because of this error during fabrication, the terminal density of devices to be mounted on the wiring board or the terminal density connecting between the wiring board and an external circuit (i.e., a reduction in the terminal pattern size) is limited. For example, in a square-shaped thick-film wiring board having a side length of 100 mm, if it is assumed that the wiring pattern contains a fabrication error of 0.2% with respect to an expected size, the spacing between a pad provided on one end of the board and a pad provided on a second end will be dislocated (e.g., deviated) from a designed value by up to 0.2 mm. Therefore, when pads for external circuits are arranged on outer regions of a wiring board, the spacing between the pads must be great enough to absorb the fabrication error (e.g., on the order of approximately 0.4 mm for a fabrication error of 0.2 mm).
Similarly, when pads for a square device have a side length of 10 mm are arranged on the wiring board, the terminal spacing likewise contains a fabrication error of up to 0.02 mm and therefore the terminal spacing must be designed to absorb the fabrication error.
As described above, the fabrication error caused by contraction during baking, in a large-size board (e.g., a board having a length of 100 mm), the board wiring lattice must be large (e.g., approximately a 0.4 mm pitch), although the basic wiring lattice is small (e.g., approximately a 0.1 mm pitch). Consequently, in the conventional wiring board, high density wiring patterns (e.g., less than about 0.4 mm) or pads (e.g., more than 200) cannot be obtained.